The subject matter relates to a semiconductor memory device; more particularly, to a phase locked loop with a delay cell for controlling a time taken for an input signal to be output using a control voltage.
Generally, semiconductor memory devices, such as a double data rate synchronous DRAM, use an external clock as a reference for conforming with various operating timings. However, after the external clock is input to the semiconductor memory device, a clock skew may be introduced by delays in internal circuits through which the external clock passes. The semiconductor memory device is provided with a clock synchronization circuit to compensate for clock skew. The clock synchronization circuit generally includes a phase locked loop (PLL) or a delay locked loop (DLL). The semiconductor memory device transmits data to external devices using an internal clock CLK_INN output by the clock synchronization circuit.
When the frequency of the internal clock CLK_INN is different from an external clock, a PLL is used as a clock synchronization circuit because it provides a frequency multiplexing function. When the internal clock CLK_INN has substantially the same frequency as an external clock, a DLL is usually used. A PLL and a DLL have substantially similar structures. However, with respect to generating the internal clock CLK_INN, a PLL using a voltage controlled oscillator is distinguished from a DLL using a voltage delay line.
FIG. 1 is a block diagram illustrating a conventional phase locked loop (PLL). The conventional PLL includes a phase comparator 100, a control voltage generator 120, a voltage controlled oscillator 140 and a frequency divider 160.
The phase comparator 100 compares a reference clock CLK_REF corresponding to an external clock with a feedback clock CLK_FED output by the frequency divider 160. The control voltage generator 120 generates a control voltage V_CTR in response to an output of the phase comparator 100. The voltage controlled oscillator 140 generates an internal clock CLK_INN in response to the control voltage V_CTR with a frequency corresponding to the control voltage V_CTR. The frequency divider 160 generates a feedback clock CLK_FED by dividing the internal clock CLK_INN. The PLL generates the control voltage V_CTR in response to a phase difference detected between the reference clock CLK_REF and the feedback clock CLK_FED, and then generates the internal clock CLK_INN with a frequency corresponds to the level of the control voltage V_CTR.
FIG. 2 is a schematic circuit diagram illustrating the voltage controlled oscillator 140 described in FIG. 1. The voltage controlled oscillator 140 includes a plurality of delay cells 200, 220, 240 and 260 connected in series, each receiving the control voltage V_CTR.
The first to fourth delay cells 200, 220, 240 and 260 respectively control an output delay for an input signal according to the control voltage V_CTR. For example, assuming that each of the delay cells 200, 220, 240 and 260 has a delay value of tD corresponding to the control voltage V_CTR, the signal input to the voltage controlled oscillator 140 is delayed by a period 4 tD after passing through the delay cells 200, 220, 240 and 260. Accordingly, when the delay value to decreases according to the control voltage V_CTR, the internal clock CLK_INN is output with a higher frequency. Alternatively, the internal clock CLK_INN is output with a lower frequency corresponding to a converse change in the control voltage V_CTR.
FIG. 3 is a schematic circuit diagram illustrating a delay cell described in FIG. 2. Because the plurality of delay cells 200 to 260 have substantially the same structure, only one delay cell is described in detail.
In the delay cell, a control voltage V_CTR determines a time taken for differential input signals IN and /IN to be outputted as first and second differential output signals OUT and /OUT. Assuming that the input signals IN and /IN are logic high and low levels, respectively, the second differential output signal /OUT increases to a predetermined level by a second current I2. Because a first current I1 sinks to a ground terminal VSS, the first differential output signal OUT decreases. Consequently, the differential output signals OUT and /OUT are transmitted to the next delay cell after the delay time determined by the control voltage V_CTR, which becomes one unit delay value.
If the control voltage V_CTR is decreased, the amount of the first and second currents I1 and I2 increases. The delay time taken for the differential output signals OUT and /OUT to reach a predetermined level decreases. In contrast, when the control voltage V_CTR is increased, the amount of the first and second currents I1 and I2 decreases. The delay time taken for the differential output signals OUT and /OUT to reach a predetermined level increases. Accordingly, the delay time of the delay cell is determined by the control voltage V_CTR.
FIG. 4 is a graph illustrating an output frequency FRE_VCO of the internal clock according to the control voltage V_CTR in the voltage controlled oscillator 140.
Referring to FIGS. 3 and 4, as the control voltage V_CTR increases, it strengthens the turning-off state of PMOS transistors PM1 and PM2 and the first and second currents I1 and I2 decrease. Accordingly, the output frequency FRQ_VCO of the internal clock CLK_INN decreases to the extent of a minimum output frequency FRQ_MIN.
As the control voltage V_CTR decreases, it strengthens the turning-on state of PMOS transistors PM1 and PM2 and the first and second current I1 and I2 increase more and more. Accordingly, the output frequency FRQ_VCO of the internal clock CLK_INN increases to the extent of a maximum output frequency FRQ_MAX. A change range of the output frequency FRQ_VCO according to the control voltage V_CTR is defined as a gain of the voltage controlled oscillator 140 and indicated as K_VCO in the specification. The gain K_VCO can be calculated by the following equation.
                    K_VCO        =                              FRQ_MAX            -            FRQ_MIN                                Δ            ⁢                                                  ⁢            V_CTR                                              (                  Equation          ⁢                                          ⁢          1                )            
Referring to FIG. 4, the frequency FRE_VCO output according to the control voltage V_CTR can vary due to conditions of process, voltage and temperature (PVT). Because operation speed of the PMOS and NMOS transistors in FIG. 3 is affected by the condition of PVT, the delay time of the delay cell can vary even under an identical control voltage V_CTR. Thus, the generated output frequency FRQ_VCO is sensitive to the conditions of PVT.
The conditions of PVT determining the output frequency FRQ_VCO are classified in this disclosure into three types of cases: TYPICAL, FAST and SLOW. When the operation speed of the PMOS and NMOS transistors is typical, the condition of PVT is a typical case, i.e., the type TYPICAL. When the operation speed of the PMOS and NMOS transistors is faster than the typical case, the condition of PVT is a fast case, i.e., the type FAST. When the operation speed of the PMOS and NMOS transistors is slower than the typical case, the condition of PVT is a slow case, i.e., the type SLOW. In FIG. 4, the linear graph PVT_T represents the output frequency FRQ_VCO according to the control voltage V_CTR in the typical case, the linear graph PVT_F represents the output frequency FRQ_VCO according to the control voltage V_CTR in the fast case, and the linear graph PVT_S represents the output frequency FRQ_VCO according to the control voltage V_CTR in the slow case.
Accordingly, an unintended output frequency FRQ_VCO may be generated or the voltage controlled oscillator 140 may have an unintended characteristic due to the condition of PVT even if the voltage controlled oscillator 140 is designed to generate the output frequency FRQ_VCO within a predetermined range. That is, as the condition of PVT changes from the typical case to the fast case, the voltage controlled oscillator 140 which is designed to output a target range for output frequency FRQ_VCO (FRQ_MAX-FRQ_MIN) according to the change of the control voltage V_CTR (ΔV_CTR) in the typical case, it outputs the output frequency FRQ_VCO out of the target range, as the output frequency FRQ_VCO changes more in response to the changes in the control voltage V_CTR (ΔV_CTR). Accordingly, the jitter characteristic of the output signal of the voltage controlled oscillator 140, i.e., the internal clock CLK_INN, deteriorates.
In the slow case, the output frequency FRQ_VCO changes less in response to the changes in the control voltage V_CTR (ΔV_CTR). While the jitter characteristic of the output signal of the voltage controlled oscillator 140 is improved, the voltage controlled oscillator 140 outputs only part of the target range for the output frequency FRQ_VCO. The voltage controlled oscillator 140 in the slow case cannot output the other part of the range.
In addition, semiconductor memory devices are required to operate faster and the maximum value of the output frequency FRQ_VCO is required to be higher. However, by expanding the target range for the output frequency FRQ_VCO in response to the control voltage V_CTR, it causes a problem that the output frequency FRQ_VCO becomes more sensitive to minor fluctuations of the control voltage V_CTR. Accordingly, the jitter characteristic of the internal clock CLK_INN deteriorates.